1. Field of the Invention
This invention relates generally to modeling circuits, and more particularly to modeling cells for hierarchical powergrid analysis.
2. Description of the Related Art
Due to the complexity of modern integrated circuits, it is often impractical to simulate the power integrity of an entire device (e.g. microprocessor) at one time. To reduce the complexity of performing such a power integrity analysis, sometimes referred to as a powergrid analysis, a hierarchical representation of the integrated circuit device may be generated. The hierarchical representation involves generating simplified models of portions of the integrated circuit device. The simplified models are then put into a higher level model of the integrated circuit device, allowing the entire device to be analyzed during a single process. Consequently, if a hierarchical powergrid analysis is to be accurate, the simplified models of the circuit portions, or cells, should also be accurate.
A full powergrid analysis of an integrated circuit device usually also includes back calculating the circuit cell's internal node voltages, resistor currents, or the like, from actual port voltages determined at a later time in the design process. Any model of a circuit cell, therefore should ideally be simple and accurate, and provide for easy back calculation.
Various modeling techniques have been used to model circuit cells for use in a hierarchical powergrid analysis. One group of such techniques, commonly referred to as Time Constant Equilibration Reduction (TICER), involve eliminating internal nodes based on time-constants. While TICER can provide adequate results in some cases, it may be less than perfect under other circumstances. For example, TICER does not necessarily produce a circuit cell model with maximum simplicity. Additionally, back calculation with TICER models can be difficult. It should be apparent, therefore, that improved techniques for modeling circuit cells for hierarchical powergrid analysis would be advantageous.